Report date: Apr 16, 2024
Conflict count: 351559
Publisher: Inderscience Enterprises Ltd.
Title count: 329
Conflict count: 3294


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Created: 2017-02-09 07:30:03.0
ConfID: 5203775
CauseID: 1402023744
OtherID: 1401880835
JT: International Journal of Circuits and Architecture Design
MD: Selma, 2 ,2,118,2016,GF(2<SUP align="right">m</SUP>) versatile multiplier/adder architecture for cryptographic applications
DOI: 10.1504/IJCAD.2016.10003046(Journal) (5203775-N )
DOI: 10.1504/IJCAD.2016.082141(Journal)
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Created: 2017-02-09 07:30:03.0
ConfID: 5203777
CauseID: 1402023744
OtherID: 1401880857
JT: International Journal of Circuits and Architecture Design
MD: Anitha, 2 ,2,169,2016,Design of PVT compensated current starved ring oscillator
DOI: 10.1504/IJCAD.2016.10003051(Journal) (5203777-N )
DOI: 10.1504/IJCAD.2016.082146(Journal)
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Created: 2018-02-06 07:30:04.0
ConfID: 5335487
CauseID: 1421445905
OtherID: 1420916198
JT: International Journal of Circuits and Architecture Design
MD: Mohan, 2 ,3/4,183,2016,Performance improvement in tree multiplier using full swing GDI logic based CLA adder
DOI: 10.1504/IJCAD.2016.10010686(Journal) (5335487-N )
DOI: 10.1504/IJCAD.2016.089640(Journal)
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Created: 2018-02-06 07:30:04.0
ConfID: 5335489
CauseID: 1421445905
OtherID: 1420916200
JT: International Journal of Circuits and Architecture Design
MD: Nazir, 2 ,3/4,201,2016,An efficient realisation of FIFO buffers for NoC routers using technology dependent optimisations targeting LUT based FPGAs
DOI: 10.1504/IJCAD.2016.10010688(Journal) (5335489-N )
DOI: 10.1504/IJCAD.2016.089643(Journal)
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Created: 2018-02-06 07:30:04.0
ConfID: 5335491
CauseID: 1421445905
OtherID: 1420987600
JT: International Journal of Circuits and Architecture Design
MD: Govindasamy, 2 ,3/4,258,2016,Real-time implementation of various colour space models
DOI: 10.1504/IJCAD.2016.10010736(Journal) (5335491-N )
DOI: 10.1504/IJCAD.2016.089654(Journal)